Forty Years of Personal Computing - MC6809

The bare board that held the HB 6809 V1 circuitry. 
Waiting for the next SS-50 project.

In computings early days, advancements happened quickly. Which mean purchases went out of date quickly. I built my SWTPc 6800 Computer System in November of 1977. In 1978, Motorola introduced the MC6809 processor, and by March 1979, SWTPc had the MP-09 CPU board available.

MC6809

For those who programmed the MC6800, the MC6809 fixed many problems. It sports 16-bit arithmetic operations, more index registers, many additional addressing modes and a very orthogonal instruction set. It was a powerhouse of an 8-bit processor. Early chips were costly, and the marketplace moved quickly beyond 8-bit chips to 16-bit ones. The MC6809 never became popular enough to dominate the market. For that brief time in the late 70s, it was the most powerful 8-bit processor. I wanted one.

Georgia Tech Symposium

In early 1983, Georgia Tech hosted a symposium where Terry Ritter, one of the designers of the MC6809 spoke. I attended, and the room was packed. Ritter talked about the design decisions that went into the architecture of the MC6809, about the importance of reusable software and position-independent code. Their design lead to the creation of BASIC09 and OS-9.

At the time, I wasn't much interested in any variety of BASIC, so I didn't pay much attention to OS-9. I should have.

The last of Ritter's talk was about an unannounced product, termed the General Motors Custom Microprocessor (GMCM). It built on the foundations of the MC6800. At that time, GM was using the MC6802 in their vehicles. The GMCM added some features to the MC6800, such as 16-bit arithmetic, an extra index register and both multiply and divide instructions. (Divide was something that the MC6809 did not have) But the GMCM lacked all the complex, orthogonal addressing modes of the MC6809. The next year, Motorola introduced the MC68HC11.

MP-09

SWTPc offered the MC6809 with the MP-09 board. The MP-09 draws from the design of the MC6800-based MP-A2 board. Both have four 2716-compatable sockets that can hold 2 KB ROM, PROM or EPROMs. While the primary difference is the CPU, there are other differences:

• SS-50 bus changes for the 6809 processor
• NMI and RESET switch connections relocated to a CPU board connector, which frees up two bus lines for BUSY and M.RDY, respectively
• ROM socket at address F800
• ROM/RAM sockets at address E000, E800, and F000
• No on-board RAM. (the MP-A and MP-A2 had 128 bytes of RAM)
• 16 bytes of writable memory at address FFFx that translate the top 4 bits of address

This last feature is known as the Dynamic Address Translator or DAT. The DAT uses a fast 16x4 bit RAM - the 74LS189 chip. It sits between the top 4 address lines A12-A15 of the CPU and the physical bus. Thus it translates address values in 4KB blocks. It is the reason the MP-09 has no on-board RAM. The ROM monitor SBUG-E, on reset, scans addresses to determine which 4 KB blocks have RAM. It then writes the DAT to position those 4 KB blocks as desired. The first block is relocated at D000-DFFF, and the second block at C000-CFFF. These two blocks are used for the stack, and any operating system such as Flex09. The rest of the memory blocks are arranged from address 0000 upward.

The board has a socket for an additional 74LS189 chip for the DAT, which adds the four higher-order bits to the DAT RAM. This extends the address bus with four more lines (S0-S3) allowing the MC6809 to address 1 MB of memory. The S0-S3 lines take the place of the bit rate signals on the SS-50 bus, so these signals have to be supplied elsewhere for the SS-30 bus. SWTPc did this with their MP-MB motherboards, a component of the SWTPc S/09 systems.

The MP-09 board runs on the original MP-B/B2 motherboards with modifications. More on these later. 

During my years in college, I eagerly wanted to upgrade my computer to the MC6809. I obtained a copy of the SBUG-E source code and studied it. By April of 1981, I modified SBUG-E, removing code for features I didn't need and adding some features of my own. I called my monitor BBUG. I used a cross-assembler on the Pr1me minicomputers to build my code. But I could not run BBUG without hardware.

MC6809E V1

My last months at Georgia Tech, I took a required course that involved building a working microprocessor system. It had to have ROM, RAM and I/O. Many of my colleagues used the computing laboratory that provided prototyping plugboards and components for their circuits.

This was a challenging course for many computer science majors. It was their first experience with digital logic. And the prototyping plugboards had been used and re-used so many times that their connections were not always reliable. This made it difficult to determine if problems were programming bugs, wiring errors, or just flakiness in the hardware.

I didn't relish dealing with flaky prototyping boards. I had fulfilled many of the requirements of this class when I built the SWTPc 6800 system in 1977! This seemed an opportunity to create my own MC6809 processor board.

I had read  articles about the MP-09, and had copies of the schematics, which I studied in-depth. There were  electronic parts stores and friends around Atlanta where I could obtain components. It seemed right.

MC6809 V1 Design

April 1983, I drew up schematics. My design borrowed from the MP-09, and included the DAT, but there were several differences.

I did not include an MC14411 bit rate generator or crystal. I intend to use extended physical memory right away. I moved the bit rate generator and crystal to a card plugged into the SS-30 bus. There were no bit rates on my SS-50 bus, only S0-S3 address lines.

Instead of the MC6809 chip, I opted to use the MC6809E. The MC6809 has a built-in clock oscillator and bus control logic. The MC6809E requires an external oscillator as well as a few chips to handle bus control for things like DMA. In trade, it has an LIC (Last Instruction Cycle) and AVMA (Advance VMA) pins. I made use of AVMA in my design.

Instead of four 2716-compatible 2KB sockets, I only had two. A ROM at Address F800, and ROM or RAM at address F000. Having ROM or RAM at E800 or E800 didn't make sense to me, since those addresses conflicted with the I/O ports used by SBUG-E. (In October 1986, I would revise this board to use a single 2732-compatible 4KB chip, covering F000-FFFF)

The memory map for this design was pretty straightforward:

• 0000-EFFF - accessing off the CPU board to the SS-50 bus
• F000-F7FF - ROM/RAM socket #1
• F800-FFFF reads - ROM socket #2
• FFF0-FFFF writes - DAT RAM

I had no option switches or jumpers in this design. It was exactly how I wanted.

Dynamic RAM Design

The same month, I drew diagrams for dynamic RAM boards. One was a 64 KB board using  4116 chips. Another design provided 256 KB memory using 4164 chips. I intended to add one of these boards to my project. The 4116 design was complicated, with multiple voltages involved. The 4164 design was simpler, but the chips were more expensive. I never build either design.

MC6809E V1 Building

Although I had made some simple PC boards, creating one for the MC6809 design was outside my skill set. Plus, it would have been expensive for my student budget. I had constructed a seven-chip CMOS keyer in 1979 using point-to-point wiring. That was difficult. I built a duplicate keyer for my brother in 1980 using wire-wrap construction. Wire-wrap was a heck of a lot easier. Plus, I already had the tools. A friend supplied wire-wrap wire and sockets and I was in business.

Wiring a design this complex directly from the schematic worried me. Wiring mistakes were easy to make, and hard to track down. Then a classmate asked to join my project. Denise Messerschmidt worked with me in the Users Assistance office at the Computer Center, and she didn't want to have to fuss with the flaky prototype boards either. She asked if she could help, and I figured should could do the wiring of the hardware. This required good instructions.

I solved that problem with a bit of software. I used the LL(1) parser generator written by fellow student Roy Mongiovi and defined a 28 production computer "language" that described the chips and devices and the wiring between them. Given a well-described design, my program produced three lists as output.

The device list showed each device and all of the signals connected to each pin. A device was either a chip or a plug. Chips listed two pins to a line, just as it would appear on a DIP device. Plugs listed one pin to a line. The device list made it easy to verify the design was correctly programmed in the language.

A cross-reference list related the signals connected to each device. Another cross-reference list showed the signals by each device and pin. One would follow this final list to do the wiring. The Wire Wrap parser was about 2500 lines of Pascal code, and it worked beautifully.

The board used 0.1" perf-board, cut to 8 1/2" by 5" -- a little smaller than standard SWTPc boards. Molex connectors epoxied on the edge connected to the SS-50 bus. I installed the wire wrap sockets, and wired up the voltage regulator and the SS-50 pins,  plus a handful of discrete components. That took care of everything that required soldering. After training Denise in wire-wrap technique, I gave her the board, wire, tools and the wiring list.

About two weeks later, she came back with the finished product. Every wire had to be manually stripped and wrapped. Denise had done an excellent job - better than I would have. 

MP-B Modifications

The MP-B motherboard required modification to work with my 6809 CPU board. The I/O ports on the MP-B decode as eight, four byte ports starting at address 8000. The SBUG-E (and hence BBUG) monitor expects eight, sixteen byte ports starting at address E000.

The modifications aren't difficult:

• Connect SS-50 A2 and A3 to SS-30 UD3 and UD4, respectively
• Move the ABC inputs in U3 from SS-50 A2, A3 and A4 to A4, A5 and A6, respectively
• Cut the trace on U3 pin 5 (Enable*) and connect to SS-50 A9
• U5 has an unused NOR gate, connect the inputs to SS-50 A10 and A11, and the output to U3 pin 6 (Enable)
• Move the U6 pin 4 (Enable*) from SS-50 bus A6 to A12
• Move the U6 decode output on pin 4 (4*) to pin 7 (7*) this signal goes to U3 pin 3 (Enable*) and  U5 pin 13 (Enable* for data bus drivers)

Modifications on underside of
MP-B. The brown wires on the 
right go to the 74LS21.

To support extended addressing using S0-S3, the traces between the SS-50 bus to the SS30 bus for the bit rate lines 110, 150, 300, 600 and 1200 must be cut. 

I added extended address decoding for the I/O ports. I mounted a 74LS21 4-input AND gate on a daughter board, and connected the inputs to S0-S3, the output goes to U6 pin 6 (Enable).

With these modifications in place, the I/O ports show up in memory as eight, sixteen byte ports, from physical address FE000 to FE1FF. The ports show up in memory four times in sequence, because address lines A7 and A8 are not decoded. 

Bit Rate Generator

Bit Rate Generator Board

Since I used the extended addressing lines S0-S3 on the SS-50 bus, the bit rate signals must be provided on the SS-30 bus. 

For this, I built a simple card that had just four components: MC14411, LM341-5 regulator, 1.8432 MHz crystal and a capacitor. You can see them lined up on the left side of the board. The MC14411 is the original device from the MP-A CPU board with a date code of 7718 - the 18th week of 1977.

Later, I added the MC6840 timer chip and the SN74LS04. At some point, this board also held an Intel 8250 UART, which is the reason for the molex connector in the upper right. But those parts have been removed. There's certainly room for an MC6850 ACIA or other I/O device on this board.

Bit rates are configured as follows:

• 110 = 38400 baud
• 150 = 2400 baud
• 300 = 300 baud
• 600 = 9600 baud
• 1200 = 1200 baud

This represents a good collection of rates across a wide range. As configured other rates are available on the MC14411 from 300 to 115200 baud.

MC6809E V1 Debugging

The beautifully wrapped board Denise wired didn't work.

When I built the SWTPc 6800 Computer System, it didn't work the first time, either. I borrowed an oscilloscope and figured out the issues. For the SWTPc 6800 boards, the problem was nearly all solder bridges. But those boards started with a working design. Mine was untested.

I had access to test equipment on campus, but I couldn't take any of it with me. I had to bring the whole computer and terminal into one of the computer center labs in the evenings, when the labs weren't in use. An oscilloscope wasn't enough. I was introduced to a new device, an HP logic analyzer -- although it took me a while to figure it out. Those evening sessions in the lab were very productive.

Dragging my computer and terminal in and out of he lab each day, I isolated six different wiring errors on the board. Had Denise let me down? No, the wiring errors were all in the original wiring listing! Denise had done her job to perfection -- she wired it exactly as specified. 

Once the wiring errors were fixed, the debugging process went smoother. I also had to correct some defects in BBUG. At one point, I had all 24 channels of the HP logic analyzer engaged. 16 pins went to the address bus, and the other 8 to the data bus. This way, I could watch each memory cycle of the MC6809 and determine what was happening.  

Eventually, I fixed the issues and had the system running. I received an "A" for the course. Denise, because of her limited involvement, received a "B", but we were both happy.

End of an Era

In 1988, I built another MC6809 CPU board. It replaced the V1 board, and once working, I stripped the V1 board down for parts. All that is left is a board with edge connectors and a voltage regulator, which you see at the beginning of the article.